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The first stage is a non-inverting stage with gain A1 and includes a local feed-forward compensation capacitor CF ; the second stage is an inverting stage with gain A2. Note that one of the inputs of the differential stage must be bypassed by signal passage by capacitor CB. The output stage of an operational amplifier provides impedance isolation from loads by presenting high input impedance to the proceeding intermediate stage and low output impedance to the load.
To provide isolation without degrading high frequency performance, the output stage is generally designed to have low input capacitance and wide bandwidth. Voltage VQ2 is bypassed at high frequencies by capacitor CB. Voltage VQ1 is applied to the inputs of a differential intermediate gain stage which consists of devices Q3, Q4, Q5 and Q6 and a current mirror which consists of devices Q7 and Q8. This stage provides additional voltage gain at low frequencies, the higher frequencies being fed forward around the intermediate circuitry by feed-forward capacitor CF.
It is necessary for stability that the drive to this stage, as supplied by the input stage, be essentially single-ended at high frequency; hence the need for bypass capacitor CB. Capacitor CB is often large in value and difficult to integrate on a chip.
Its action discards 6dB of high frequency voltage gain. Thus, the prior art has limitations when applied to low voltage designs and the level of circuit complexity is too great for use in cost-effective, multiple-amplifier-on-a-chip products.
It is an object of the present invention to provide a single input CMOS gain stage that operates on low voltage. It is a further object of the invention to provide a feed-forward gain stage that does not require an additional compensation capacitor for input signal bypassing. These and other objects of the invention are accomplished by providing a single-input, single-ended, feed-forward gain stage which includes means for feeding the input signal forward to a high impedance node at the output at high frequency.
The frequency at which this occurs is set to be lower than the unity gain frequency of the overall amplifier of which the gain stage is a part. The ground referred input of the gain stage is a simple interface to low voltage circuitry, while the rail-to-rail output swing makes maximum use of low supplies. Other objects, features and advantages of the present invention will become apparent and be appreciated by referring to the detailed description provided below which is to be considered in conjunction with the accompanying drawings.
The output of gain stage 14 is provided to an inverting gain stage 16 having gain -A2. The output of gain stage 16 is provided to a unity gain output stage 18 which generates output signal VOUT. A feed-back path from the input of the non-inverting gain stage 14 to the output of the inverting gain stage 16 is provided through capacitor Cc to provide frequency compensation around the intermediate gain stages 14 and 16 in the conventional manner. Thus, the operational amplifier illustrated in FIG.
The primary difference is that the prior art differential approach requires an additional and large compensation capacitor CB to insure that the input stage drives the feed-forward stage in a single-ended fashion at high frequencies. This is necessary to maintain frequency stability.
In addition, the differential approach is more complex than the concept of the present invention and not as amenable to low supply voltage operation. In the embodiment of the invention shown in FIG. The source of transistor M1 is connected to ground while its drain is connected to the commonly-connected gates of current mirror transistors M2 and M3. According to the standand current mirror configuration, the drain of transistor M2 is connected to the gates of transistors M2 and M3.
This current mirror is not restricted to a gain of one; it can have any ratio, n. The drain of transistor M3 is connected to the Hi-Z node which is also connected to ground through current load I. The circuit shown in FIG. That is, the dc signal path is bypassed. Operation of the circuit shown in FIG. The output is capable of rail-to-rail swing, an important advantage in low voltage circuits. When driven from Hi-Z sources, it is often preferable to drive capacitor CF with a separate voltage follower.
The source of the PMOS transistor 11 is connected to a first voltage supply VCC, the source of the NMOS transistor 13 being grounded while the drains of the transistors 11, 13 are connected to an output A signal applied to input node 12 of the first inverter 10 is inverted at the output The inverted signal is then reinverted by the inverter The source of the PMOS transistor 16 is connected to a second voltage supply VDD characterized by a higher voltage than the first voltage supply so that the re-inverted signal at output node 18 of the second inverter 15 has a peak voltage shifted up or increased with respect to the peak voltage of the signal at the input node During each transition of the signal at the input node 12 between 0 volts and its peak voltage 5 volts, for example , both of the transistors 16 and 17 in the second inverter 15 may be on, but after such a transition is finished one or the other of the transistors 16, 17 should be off virtually non-conducting in order to prevent direct current power dissipation from the voltage supply VDD to ground.
The disadVantage of the level shifter circuit of FIG. With both transistors on, a path exists permitting DC power dissipation, a significant problem. However, a significant disadvantage of the level shifter circuit of FIG. The level shifter of FIG. Because not all the transistors of the complementary transistor pairs in the latch circuit 45 will be turned on after each transition of the input signal, there is no direct current path from the voltage supply VDD to ground.
This feature solves the problem of DC power consumption. However, another problem exists in that two power supplies VCC and VDD characterized by different voltages are required to perform voltage level shifting. Gate 63 of the NMOS transistor 62 receives a reference signal which governs the difference between the voltage at input node 59 and the voltage at output node A bias voltage VB is applied to the gate of the current source transistor The disadvantage of the level shifter of FIG.
In summary, it would seem that a voltage level shifter circuit can enjoy only one of two distinct advantages, but not both, namely that the circuit either requires only a single voltage supply or else the circuit has low DC power consumption. Thus, there is a need for a voltage level shifter circuit which provides both advantages simultaneously. The latch has two branches, each branch having a complementary NMOS and PMOS field effect transistor pair with a common drain, one of the transistors in the pair being connected to ground.
A latch transistor in each branch is connected in series between the other transistor of the complementary transistor pair and a voltage supply, the gate of the latch transistor being cross-connected to the common drain of the complementary transistor pair in the other branch. Each complementary transistor pair has a common gate, one of them being connected to the input node of the input inverter and the other being connected to the output node of the input inverter, so that the two complementary transistor pairs are in opposite states.
Whenever the one transistor in each complementary pair which is connected to ground is on, the latch transistor in the same branch is turned off by the voltage on the common drain of the other pair after each voltage transition by the input signal thus blocking the path from the voltage supply to ground. This minimizes or eliminates DC power consumption from the voltage supply to ground. A single voltage supply suffices to energize the voltage generator and the latch, no other voltage supply being required.
In the preferred embodiment of the invention, the input inverter produces an inverted signal having a lower peak voltage proportional to the voltage furnished by the voltage generator while the latch circuit responds to the inverted signal to produce a corresponding signal having a higher peak voltage proportional to the voltage of the single voltage supply.
Thus, the level shifting circuit of the invention enjoys both the advantage of requiring only a single voltage supply and the advantage of low DC power consumption. The voltage generator of the preferred embodiment includes an NMOS source follower transistor and a capacitor for reducing fluctuations in the voltage furnished by the source follower transistor.
Further, a directional switching element like a diode prevents discharge of the capacitor through the source follower transistor. The source of the PMOS transistor 78 is connected to output node 73 of a voltage generator 70 while the drain of the NMOS transistor 76 is connected to ground. Input node 79 receives the signal whose peak voltage level is to be shifted, the node 79 being connected to the gates of the complementary transistor pair 76, The complementary transistor pair 76, 78 have a common drain 77 which is the output node of the input inverter B Voltage Generator The voltage generator 70 includes an NMOS source follower transistor 71, a directional switching element 72 and a capacitor 74 all connected in series between a voltage supply VDD and ground.
The output node 73 of the voltage generator 70 is the connection between the capacitor 74 and the directional switching element The NMOS source follower transistor is a field effect transistor having its source and well or substrate connected together.
The directional switching element 72 is an NMOS field effect transistor having its gate and source connected together. The well or substrate of the NMOS source follower transistor 71 and directional switching element 72 are effectively connected together by well-known techniques. The NMOS source follower transistor 71 operates so that its source voltage follows its gate voltage.
For example, if the input node 79 is at 5 volts, then the source voltage of the NMOS source follower transistor 71 is at approximately 5-VT volts, where VT is the threshold voltage of the NMOS source follower transistor
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